1) Field of the Invention
This invention relates to a logic circuit suitable for use with a magnitude comparison circuit, a carrier production circuit, a full adder circuit and an increment circuit.
2) Description of the Related Art
A great number of magnitude comparison circuits, carry generation circuits, full adder circuits and increment circuits are used as basic circuits in a processor. The processor requires a large number of basic circuits in order to perform addition and subtraction with operation commands. For example, a magnitude comparison circuit is used for floating point arithmetic. In particular, when floating point arithmetic is performed, positioning of two parts including a characteristic and a mantissa of a numeral must be performed. Therefore, the magnitude comparison circuit is used when it is required to compare two parts of a numeral to discriminate which one of the two parts is a characteristic or a mantissa in order to perform the positioning. An adder circuit is used, in order to perform address calculation to effect load/store, to add two or three kinds of operands to determine an address to load data from a memory. A carry generation circuit is used to make it possible to perform high speed arithmetic where the bit length on an adder circuit is great. Further, an increment circuit is used principally for a command register and has an increment of several lower figures which varies at random. In this point, the increment circuit is different from an ordinary counter circuit. In particular, an increment circuit having a great bit length of 64 bits is used. Therefore, an ordinary counter such as a register is not used for the increment circuit. Further, while the counter circuit increments one by one, the increment circuit has an increment which exhibits a variation among 2, 4, 8, 16 and so forth.
Since the working speeds of such basic circuits as described above determine the processing speed of the processor, they must be constructed as circuits which operate at high speeds. However, since generally the bit widths of the circuits are different depending upon places where they are used, many kinds of magnitude comparison circuits, carrier production circuits, adder circuits and increment circuits must be developed. As the technology progresses year by year, it is demanded to efficiently develop those kinds of circuits which have different bit widths and operate at high speeds. Therefore, minimized numbers of leaf cells are required to be used to construct circuits which operate at high speeds.
The leaf cell (also called functional cell) is a cell of a hierarchy in which layout thereof must be performed on the transistor level and is a cell of the lowest layer of a module which exhibits a function. For example, a module in a hierarchy below a circuit which has a 64-bit addition function is a 16-bit adder circuit, and a module of a hierarchy below the circuit having the 16-bit addition function is a 4-bit adder circuit. And, where there is no module in a hierarchy below the circuit having the 4-bit addition function, the 4-bit adder circuit is formed from a leaf cell of the lowest hierarchy.
Now, an example of an adder circuit is described with reference to FIGS. 26 to 29 and an example of an increment circuit is described with reference to FIG. 30.
First, since a look-ahead carry full adder circuit is used for an adder circuit, the adder circuit requires a great number of parts. The look-ahead carry full adder circuit signifies a circuit which performs arithmetic using a carry generation function G and a carry propagation function P for a unit of a block which is formed from 4 groups each formed from 4 bits. The reason why the look-ahead carry full adder circuit just described is used is that a carry propagation adder circuit cannot perform high speed processing. In particular, the carry propagation adder circuit performs addition simply and propagates a carry signal successively from the lowest order figure to the highest order figure and requires excessive time for the addition. In contrast, the look-ahead carry full adder circuit is used so that processing of the carry can be performed at a high speed. This is described more specifically with reference to FIGS. 26 to 29.
FIG. 26 is a block diagram showing an example of a functional block of an 8-bit look-ahead carry full adder circuit. Referring to FIG. 26, the 8-bit look-ahead carry full adder circuit 90 shown includes a carry generation/propagation unit 91, an 8-bit CLA (look-ahead carry) unit 92 and a sum unit 93.
An 8-bit signal A [A7 A6 A5 A4 A3 A2 A1 A0] and another 8-bit signal B [B7 B6 B5 B4 B3 B2 B1 B0] are inputted to the carry generation/propagation unit 91, and a carry for each bit number n is outputted in accordance with the following expression from the 8-bit CLA unit 92:Cn+1=Cn·Pn+Gn where Gn is the carry signal, Pn is a carry propagation function, and Cn is a carry generation function. Results of the arithmetic of the 8-bit CLA unit 92 are supplied as a plurality of carries to the sum unit 93, and results of addition from the carries are outputted from the sum unit 93.
The units 91 to 93 have such constructions as shown in FIGS. 27 to 29, respectively. In particular, FIG. 27 is a block diagram showing a detailed construction of the carry generation/propagation unit 91; FIG. 28 is a block diagram showing a general construction of a 4-bit CLA unit; and FIG. 29 is a block diagram showing a general construction of the sum unit. As can be seen from FIGS. 27 to 29, each of the units includes a large number of logic gates.
Similarly, FIG. 30 is a block diagram showing a construction of a 16-bit increment circuit which employs a multi-input AND gate. Referring to FIG. 30, a gate 94 logically exclusively ORs a result of half addition arithmetic at each of the 0th to nth figures (0≦n<16) and a carry signal from the lower order figures and outputs a result of the logical exclusive ORing as a full addition arithmetic result. The “carry signal from the lower order figures” is, for example, a signal denoted by C<1> in FIG. 30, and the signal C<1> is determined as an AND value of all of the 15 bits A<1>, A<2>, A<3>, . . . , A<15> lower than the 0th figure (A<0>). Similarly, the gate 94 logically exclusively ORs a half addition arithmetic result at the first figure (A<1>) and a carry signal C<2> determined from an AND value of all of the 14 bits A<2>, A<3>, . . . , A<15>. Further, a carry signal C<13> at the 12th figure from the lower order figures is an AND value of the 3 bits A<13>, A<14>, A<15>; a carry signal C<14> at the 13th figure from the lower order figures is an AND value of the 2 bits A<14>, A<15>; and a carry signal C<15> at the 14th figure from the lower figures is a value of the 15th bit itself. Accordingly, a large number of AND gates are required to determine AND values at the individual figures.
However, since such an adder circuit or an increment circuit as described above requires many kinds of basic circuits and has a complicated structure, it has a subject to be solved in that the processing speed is low. For example, the 4-bit CLA unit shown in FIG. 28 has a complicated structure and requires many kinds of leaf cells. In particular, as seen from a broken line block, the unit shown includes ten AND gates and four OR gates, and where a multi-input gate circuit employs a NOR gate or the like to invert an OR output, the speed is retarded because a delay of propagation by one clock is caused by the NOR gate or the like. The reason is that two PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) are connected in series. Further, as seen from FIG. 30, also the increment circuit includes many basic parts and has a complicated structure with a comparatively low degree of repetitiveness of wiring lines, and consequently, many man-hours are required for the layout (arrangement) of the gates and so forth.
Meanwhile, many proposals have been made in order to raise the speed of an entire circuit. Japanese Patent Laid-Open No. 187129/1994 (hereinafter referred to as document 1) discloses a technique wherein, in order to provide a semiconductor device wherein logic circuits such as full adders and so forth having a high speed and a small circuit scale are integrated, a logic production section composed of four NMOS transistors and a latch circuit composed of two PMOS transistors are combined to form a high speed logic circuit including a small number of elements as a basic circuit and such basic circuits are combined to form several function circuits such as a full adder. The document 1, however, does not disclose a technique for expanding the function circuits.
In order to achieve reduction of the number of elements used and augmentation of the operation speed, a technique regarding a pass transistor logic circuit is disclosed in Japanese Patent Laid-Open No. 162722/1997 (hereinafter referred to as document 2). The object of the document 2 is such as follows. In particular, it is an object of the document 2 to provide a pass transistor logic circuit which exhibits an improved H level and simultaneously allows operation with a low power supply voltage without using a pull-up circuit, reduces the load to an outputting circuit in the preceding stage to achieve augmentations of the operation speed, prevention of failure in transmission of a signal to a next stage and augmentation of the resistance to noise, suppresses the number of stages of transistors in a logical arithmetic system of a logic circuit composed only of pass transistors as far as possible to augment the operation speed while comparatively complicated logic can be implemented and particularly logic which cannot be implemented readily with a logic circuit which is formed only from pass transistors can also be augmented comparatively readily, and allows implementation of a logic circuit which includes a reduced number of necessary elements and operates with a comparatively high operation speed even in comparison with an alternative circuit formed from a CMOS (Complementary Metal Oxide Semiconductor) logic circuit. According to the technique of the document 2, however, a plurality of pass transistors whose outputs exhibit on or off in response to logical values of inputs thereto are connected in series or in parallel to form a circuit which performs logical AND arithmetic or logical OR arithmetic to obtain a desired logic circuit. Therefore, the technique of the document 2 still is complicated in construction and lacks in expandability.
Different techniques relating to a pass transistor are disclosed in U.S. Pat. No. 4,566,064 (hereinafter referred to as document 3), Japanese Patent Laid-Open No. 226/1984 (hereinafter referred to as document 4) and U.S. Pat. No. 4,622,648 (hereinafter referred to as document 5). The techniques disclosed in the documents 3 to 5 have an object to provide a novel logic circuit construction method. According to the techniques of the documents 3 to 5, a pass transistor is used to form a logic circuit, and the regularity of resultant logic circuits formed in this manner is increased to the maximum. Where logic circuits obtained using the techniques are used to form a combination circuit, the combination circuit is augmented significantly in terms of the configuration, power and operation speed when compared with ordinary logic circuits. However, the documents 3 to 5 do not disclose a functional circuit such as an adder circuit, a magnitude comparison circuit, an increment circuit or a like circuit.
Meanwhile, a technique for reducing the number of transistors which form an EXOR or EXNOR circuit is disclosed in Japanese Patent Laid-Open No. 201527/1984 (hereinafter referred to as document 6) and U.S. Pat. No. 4,621,338 (hereinafter referred to as document 7) which has claimed the priority based on an application based on which also the document 6 has claimed the priority. However, the documents 6 and 7 are directed toward providing an EXOR or EXNOR circuit which requires a smaller number of transistors than an ordinary device and providing a CMOS full adder stage in which such an EXOR or EXNOR circuit is used, and do not disclose a technique relating to high speed operation or expandability.
In addition, the documents mentioned above do not disclose any technique for saving time required for tuning (adjustment) of components. In particular, where a great number of components are involved, there is a subject to be solved in that much time is required for tuning of the components. Besides, if it is tried to form adder circuits of different bit lengths for an increment circuit which are formed from adder circuits of different bit lengths such as a 64-bit adder circuit and a 4-bit adder circuit, much variation is required for circuit arrangement. Therefore, in order to evaluate a circuit ready for new technology, many basic circuits such as leaf cells must be re-evaluated and connected. Thus, there is a subject to be solved in that the efficiency in development is low.